Name
Title | ||
|---|---|---|
Design Implementation With Noninteger Multiple-Height Cells for Improved Design Quality in Advanced Nodes. |
Abstract | ||
|---|---|---|
Standard-cell libraries can be developed with different cell heights (e.g., in FinFET technology, corresponding to different numbers of fins). Larger cell heights provide higher drive strengths, but at the cost of larger area and power consumption as well as pin capacitance. Cells with smaller heights are relatively smaller in area, but have weaker drive strengths and are more likely to suffer fro... |
Year | DOI | Venue |
|---|---|---|
2018 | 10.1109/TCAD.2017.2731679 | IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems |
Keywords | Field | DocType |
Optimization,Tools,Capacitance,Routing,Delays,Pins | Row,Fin,Computer science,Flow (psychology),Design methods,Electronic engineering,Computational science,Circuit breaker,Physical design,Performance improvement,Floorplan | Journal |
Volume | Issue | ISSN |
37 | 4 | 0278-0070 |
Citations | PageRank | References |
1 | 0.36 | 0 |
Authors | ||
3 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Sorin Dobre | 1 | 37 | 4.58 |
| Andrew B. Kahng | 2 | 7582 | 859.06 |
| Jiajia Li | 3 | 317 | 34.53 |