Name
Abstract | ||
|---|---|---|
In this paper, hybrid architecture for DTCWT computation is designed and implemented on FPGA based on DA algorithm. The distributive arithmetic (DA) algorithm is combined with multiplexer based algorithm to optimize the resource utilization on configurable logic block (CLB). The filter coefficients of DTCWT are quantized, rounded to its nearest integer for DTCWT computation and the loss in rounding and quantization is limited to 0.5 dB as compared with software implementation. The parallel architecture designed computes row elements simultaneously and pipelined architecture is designed to compute column elements. The proposed architecture is modeled using Verilog and implemented on Xilinx FPGA. The design operates at a maximum frequency of 496 MHz and consumes power less than 0.2W. |
Year | DOI | Venue |
|---|---|---|
2018 | 10.1142/S0219467818500043 | INTERNATIONAL JOURNAL OF IMAGE AND GRAPHICS |
Keywords | Field | DocType |
Dual tree complex wavelets, systolic array, pipelined architecture, FPGA implementation, parallel architecture | Computer vision,Parallel computing,Field-programmable gate array,Systolic array,Multiplexer,Rounding,Artificial intelligence,Logic block,Verilog,Quantization (signal processing),Mathematics,Filter design | Journal |
Volume | Issue | ISSN |
18 | 1 | 0219-4678 |
Citations | PageRank | References |
0 | 0.34 | 8 |
Authors | ||
3 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| S. S. Divakara | 1 | 0 | 0.68 |
| Sudarshan Patilkulkarni | 2 | 2 | 2.14 |
| Cyril Prasanna Raj | 3 | 1 | 1.06 |