Title | ||
---|---|---|
A Compiler Technique for Processor-Wide Protection From Soft Errors in Multithreaded Environments. |
Abstract | ||
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Aggressive transistor scaling down and nearthreshold computing have rendered modern microprocessor susceptible to soft errors. Software approaches that protect computations against soft errors are desirable because they offer flexible protection and are suitable for mixed-critical systems. In particular, fine-grain instruction duplication based techniques are deemed to be most effective; however, ... |
Year | DOI | Venue |
---|---|---|
2018 | 10.1109/TR.2018.2793098 | IEEE Transactions on Reliability |
Keywords | DocType | Volume |
Registers,Hardware,Transient analysis,Instruction sets,Microprocessors | Journal | 67 |
Issue | ISSN | Citations |
1 | 0018-9529 | 0 |
PageRank | References | Authors |
0.34 | 0 | 2 |
Name | Order | Citations | PageRank |
---|---|---|---|
Moslem Didehban | 1 | 16 | 3.33 |
Aviral Shrivastava | 2 | 812 | 68.67 |