Paper Info
Title
Low Power Switched-Current Circuits With Low Sensitivity To The Rise/Fall Time Of The Clock
Abstract
The switched-current (SI) technique permits realizing analog discrete-time circuits in standard digital CMOS technology. A very important property of the analog part of a system on a chip is the possibility it offers for realizing some functions of a digital circuit, but with reduced power consumption. In this paper, a low power SI integrator is presented It is shown that an integrator consuming a fraction of a milliwatt can be designed in 0.35 mu m CMOS technology with the use of narrow transistor channels, and with the channel length as a design parameter. The impact of the rise/fall time of the clock signal on the integrator operation is observed. It is shown that this effect can be reduced when the proper switch dimensions are taken for the integrator. Analysis and measurements of the integrator noise are presented. The integrator was built with equal size transistors, yielding less sensitivity to variations in production parameters. An experimental chip in 0.35 mu m CMOS technology was fabricated, and measurements are compared with results obtained during analysis and simulations. In order to verify the properties of the designed integrator experimentally, a first-order filter is built with the use of elementary cells on the chip. Copynght (C) 2008 John Wiley & Sons, Ltd.
Year
DOI
Venue
2010
10.1002/cta.576
INTERNATIONAL JOURNAL OF CIRCUIT THEORY AND APPLICATIONS
Keywords
DocType
Volume
switched-current circuits, low power integrators, switched-current filters, noise
Journal
38
Issue
ISSN
Citations 
5
0098-9886
0
PageRank 
References 
Authors
0.34
0
3
Name
Order
Citations
PageRank
Radek Rudnicki100.34
Marek Kropidłowski251.79
Andrzej Handkiewicz3112.44