Name
Abstract | ||
|---|---|---|
A method for estimating integral nonlinearity (INL) in pipeline analog-to-digital converters is presented. In this method, errors in each stage are modeled by an equivalent input-referred gain error and an input-referred nonlinearity. For a switched capacitor implementation, the proposed model predicts the maximum statistical INL in terms of capacitor mismatch and also provides an exact formula for INL in terms of finite gain of operational amplifiers. Using this model, it is proved that a high per-stage resolution reduces the power consumption in low-speed converters, whereas in high-speed circuits 1.5-bit or 2.5-bit stage is more advantageous. It is also shown that when voltage swing is below I V, the lower limit for the size of the capacitors is mainly determined by thermal noise rather than by INL. Copyright (C) 2008 John Wiley & Sons, Ltd. |
Year | DOI | Venue |
|---|---|---|
2009 | 10.1002/cta.511 | INTERNATIONAL JOURNAL OF CIRCUIT THEORY AND APPLICATIONS |
Keywords | DocType | Volume |
analog-to-digital converter, pipeline ADC, integral nonlinearity (INL), switched-capacitor | Journal | 37 |
Issue | ISSN | Citations |
6 | 0098-9886 | 0 |
PageRank | References | Authors |
0.34 | 0 | 2 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Behnam Sedighi | 1 | 58 | 10.33 |
| M. Sharif Bakhtiar | 2 | 5 | 1.51 |