Title
A 4-Transistor nMOS-Only Logic-Compatible Gain-Cell Embedded DRAM With Over 1.6-ms Retention Time at 700 mV in 28-nm FD-SOI.
Abstract
Gain-cell embedded DRAM (GC-eDRAM) is a possible alternative to traditional static random access memories (SRAM). While GC-eDRAM provides high-density, low-leakage, low-voltage, and inherent2-ported operation, its limited retention time requires periodic, power-hungry refresh cycles. This drawback is further aggravated at scaled technologies, where increased subthreshold leakage currents and decre...
Year
DOI
Venue
2018
10.1109/TCSI.2017.2747087
IEEE Transactions on Circuits and Systems I: Regular Papers
Keywords
Field
DocType
Microprocessors,Random access memory,Transistors,Capacitance,MOS devices,Arrays
Silicon on insulator,Dram,NMOS logic,Data retention,Static random-access memory,Electronic engineering,Subthreshold conduction,Transistor,Mathematics,Random access
Journal
Volume
Issue
ISSN
65
4
1549-8328
Citations 
PageRank 
References 
4
0.58
0
Authors
4
Name
Order
Citations
PageRank
Robert Giterman1409.55
Alexander Fish2647.48
A. Burg31426126.54
Adam Teman412919.12