Name
Title | ||
|---|---|---|
Cache-Aware SPM Allocation to Reduce Worst-Case Execution Time for Hybrid SPM-Caches. |
Abstract | ||
|---|---|---|
Scratch-Pad Memories (SPMs) have been increasingly used in real-time and embedded systems. However, it is still unknown and challenging to reduce the worst-case execution time (WCET) for hybrid SPM-cache architecture, where an SPM and a cache memory are placed on-chip in parallel to cooperatively improve performance and/or energy efficiency. In this paper, we study four SPM allocation strategies to reduce the WCET for hybrid SPM-caches with diffierent complexities. These algorithms differ by whether or not they can cooperate with the cache or be aware of the WCET. Our evaluation shows that the cache-aware and WCET-oriented SPM allocation can minimize the WCET for real-time benchmarks with little or even positive impact on the average-case execution time (ACET). |
Year | DOI | Venue |
|---|---|---|
2018 | 10.1142/S0218126618500809 | JOURNAL OF CIRCUITS SYSTEMS AND COMPUTERS |
Keywords | Field | DocType |
SPM,cache memories,WCET,real-time systems | Architecture,Worst-case execution time,Cache,Computer science,CPU cache,Efficient energy use,Parallel computing,Execution time,Embedded system | Journal |
Volume | Issue | ISSN |
27 | 5 | 0218-1266 |
Citations | PageRank | References |
3 | 0.45 | 24 |
Authors | ||
2 | ||