Title
SAT-based reverse engineering of gate-level schematics using fault injection and probing
Abstract
Gate camouflaging is a known security enhancement technique that tries to thwart reverse engineering by hiding the functions of gates or the connections between them. A number of works on SAT-based attacks have shown that it is often possible to reverse engineer a circuit function by combining a camouflaged circuit model and the ability to have oracle access to the obfuscated combinational circuit. Especially in small circuits it is easy to reverse engineer the circuit function in this way, but SAT-based reverse engineering techniques provide no guarantees of recovering a circuit that is gate-by-gate equivalent to the original design. In this work we show that an attacker who doesn't know gate functions or connections of an aggressively camouflaged circuit cannot learn the correct gate-level schematic even if able to control inputs and probe all combinational nodes of the circuit. We then present a stronger attack that extends SAT-based reverse engineering with fault analysis to allow an attacker to recover the correct gate-level schematic. We analyze our reverse engineering approach on an S-Box circuit.
Year
DOI
Venue
2018
10.1109/HST.2018.8383918
2018 IEEE International Symposium on Hardware Oriented Security and Trust (HOST)
Keywords
DocType
Volume
gate-level schematics,gate camouflaging,camouflaged circuit model,obfuscated combinational circuit,reverse engineering techniques,gate-by-gate equivalent,gate functions,reverse engineering approach,S-Box circuit
Conference
abs/1802.08916
ISBN
Citations 
PageRank 
978-1-5386-4732-5
2
0.36
References 
Authors
15
5
Name
Order
Citations
PageRank
Shahrzad Keshavarz1102.23
Falk Schellenberg2276.05
Bastian Richter3133.75
Christof Paar43794442.62
Daniel E. Holcomb546231.63