Title
TimingCamouflage: Improving circuit security against counterfeiting by unconventional timing
Abstract
With recent advances in reverse engineering, attackers can reconstruct a netlist to counterfeit chips by opening the die and scanning all layers of original chips. This relatively easy counterfeiting is made possible by the use of the standard simple clocking scheme where all combinational blocks function within one clock period. In this paper, we propose a method to invalidate the assumption that a netlist completely represents the function of a circuit. With the help of wave-pipelining paths, this method forces attackers to capture delay information from manufactured chips, which is a very challenging task because we also introduce false paths. Experimental results confirm that wave-pipelining paths and false paths can be constructed in benchmark circuits successfully with only a negligible cost, while the potential attack techniques can be thwarted.
Year
DOI
Venue
2018
10.23919/DATE.2018.8341985
2018 Design, Automation & Test in Europe Conference & Exhibition (DATE)
Keywords
Field
DocType
TimingCamouflage,circuit security,unconventional timing,reverse engineering,standard simple clocking scheme,combinational blocks function,clock period,wave-pipelining paths,delay information,potential attack techniques
Netlist,Logic gate,Computer science,Parallel computing,Reverse engineering,Computer hardware,Counterfeit,Electronic circuit
Conference
ISSN
Citations 
PageRank 
1530-1591
3
0.37
References 
Authors
0
5
Name
Order
Citations
PageRank
Grace Li Zhang1133.68
Bing Li217233.77
Bei Yu365674.07
David Z. Pan42653237.64
Ulf Schlichtmann510921.56