Name
Abstract | ||
|---|---|---|
Resistive RAMs (ReRAMs) have gained prominence for design of logic-in-memory circuits and architectures due to fast read/write speeds, high endurance, density and logic operation capabilities. ReRAM crossbar arrays allow constrained bit-level parallel operations. In this paper, for the first time, we propose optimization techniques during logic synthesis, which are specifically targeted for leveraging the parallelism offered by ReRAM crossbar arrays. Our method uses Majority-Inverter Graph (MIG) for the internal representation of the Boolean functions. The novel optimization techniques, when applied to the MIG, exposes the hit-level parallelism, and is further coupled with an efficient technology mapping flow. The entire synthesis process is benchmarked exhaustively over large arithmetic functions using a representative ReRAM crossbar architecture, while varying the crossbar dimensions. For the hard benchmarks, we obtained 10% reduction in the number of nodes with 16% reduction in delay on average. |
Year | Venue | Field |
|---|---|---|
2018 | PROCEEDINGS OF THE 2018 DESIGN, AUTOMATION & TEST IN EUROPE CONFERENCE & EXHIBITION (DATE) | Boolean function,Logic synthesis,Arithmetic function,Computer science,In-Memory Processing,Parallel computing,Electronic circuit,AND gate,Crossbar switch,Resistive random-access memory |
DocType | ISSN | Citations |
Conference | 1530-1591 | 0 |
PageRank | References | Authors |
0.34 | 0 | 3 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Debjyoti Bhattacharjee | 1 | 26 | 9.84 |
| Luca Amarú | 2 | 206 | 28.41 |
| Anupam Chattopadhyay | 3 | 6 | 4.23 |