Name
Title | ||
|---|---|---|
Examining The Consequences Of High-Level Synthesis Optimizations On Power Side-Channel |
Abstract | ||
|---|---|---|
High-level synthesis (HLS) allows hardware designers to think algorithmically and not have to worry about lowlevel, cycle-by-cycle details. This provides the ability to quickly explore the architectural design space and tradeoff between resource utilization and performance. Unfortunately, evaluating the security is not a standard part of the HLS design flow. In this work, we aim to understand the effects of HLS optimizations with respect to power side-channel leakage. We use Vivado HLS to develop different cryptographic cores, implement them on a Xilinx Spartan 6 FPGA, and collect power traces. We evaluate the designs with respect to resource utilization, performance, and side-channel leakage through power consumption. Furthermore, we analyze the first-order leakage of the HLS-based designs alongside well-known register transfer level (RTL) cryptographic cores. We describe an evaluation procedure for hardware designers and use it to make insightful recommendations on how to design the best architecture in cryptographic domain. |
Year | Venue | Field |
|---|---|---|
2018 | PROCEEDINGS OF THE 2018 DESIGN, AUTOMATION & TEST IN EUROPE CONFERENCE & EXHIBITION (DATE) | Spartan,Cryptography,Computer science,Parallel computing,High-level synthesis,Field-programmable gate array,Design flow,Side channel attack,Register-transfer level,Benchmark (computing),Embedded system |
DocType | ISSN | Citations |
Conference | 1530-1591 | 0 |
PageRank | References | Authors |
0.34 | 9 | 7 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Lu Zhang | 1 | 163 | 40.09 |
| Wei Hu | 2 | 3 | 1.04 |
| Armaiti Ardeshiricham | 3 | 11 | 2.90 |
| Yu Tai | 4 | 9 | 5.92 |
| Jeremy Blackstone | 5 | 3 | 2.43 |
| Dejun Mu | 6 | 21 | 5.56 |
| Ryan Kastner | 7 | 1779 | 147.73 |