Paper Info
Title
Task Scheduling For Many-Cores With S-Nuca Caches
Abstract
A many-core processor may comprise a large number of processing cores on a single chip. The many-core's last-level shared cache can potentially he physically distributed alongside the cores in the form of cache banks connected through a Network on Chip (NoC). Static Non-Uniform Cache Access (S-NUCA) memory address mapping policy provides a scalable mechanism for providing the cores quick access to the entire last level cache. By design, S-NUCA introduces a unique topology based performance heterogeneity and we introduce a scheduler that can exploit it. The proposed scheduler improves performance of the many-core by 9.93% in comparison to a state-of-the-art generic many-core scheduler with minimal run-time overheads.
Year
Venue
Field
2018
PROCEEDINGS OF THE 2018 DESIGN, AUTOMATION & TEST IN EUROPE CONFERENCE & EXHIBITION (DATE)
Shared memory,Cache,Scheduling (computing),Computer science,Instruction set,Parallel computing,Network on a chip,Chip,Memory address,Scalability
DocType
ISSN
Citations 
Conference
1530-1591
0
PageRank 
References 
Authors
0.34
0
2
Name
Order
Citations
PageRank
Anuj Pathania118114.97
J. Henkel24471366.50