Name
Abstract | ||
|---|---|---|
As the memory wall issue continues in the era of big data, researchers have been exploring emerging technologies to replace or complement the current DRAM based main memory system. Among them, Multi-Level Cell (MLC) configurations of Spin-Transfer Torque Random Access Memory (STT-RAM) attracts tremendous interests and has been deployed as the onchip cache successfully. In this paper, we discuss the possibilities and challenges of employing MLC STT-RAM in the future persistent memory system. We also propose a hybrid data block to bit mapping strategy called Double-S to promote the use of soft bit in MLC. In the end, we evaluate the power consumption and IPC of MLC based main memory system and conclude that MLC can significantly reduce the overall energy dissipation. To unleash the potential of MLC as the main memory, architecture support such as MLC as memory extension is required in the future deployment. |
Year | Venue | Field |
|---|---|---|
2017 | DASC/PiCom/DataCom/CyberSciTech | Memory wall,Dram,Software deployment,Cache,Computer science,Memory management,Non-volatile memory,Big data,Embedded system,Random access |
DocType | Citations | PageRank |
Conference | 0 | 0.34 |
References | Authors | |
0 | 3 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Xunchao Chen | 1 | 4 | 2.44 |
| Jun Wang 0001 | 2 | 19 | 6.11 |
| Jian Zhou | 3 | 10 | 10.43 |