Name
Abstract | ||
|---|---|---|
Many today's real-time applications, such as Advanced Driver Assistant Systems (ADAS), demand both high computing power and safety guarantees. High computing power can be easily delivered by, now ubiquitous, multi-core CPUs or by a heterogeneous system with a multi-core CPU and a parallel accelerator such as a GPU. Reaching the required safety level in such a system is by far more difficult because the commercial-of-the-shelf (COTS) high-performance platforms contain many shared resources (e.g. main memory) with arbiters not designed to provide real-time guarantees.A promising approach to address this problem, known as PRedictable Execution Model (PREM), was introduced by Pellizzoni et al. [1]. We are interested in applying PREM to ARM-based heterogeneous platforms, but so far, all PREM-related work has been done on x86 or PowerPC. In this paper, we introduce several building blocks that are needed for implementing PREM on NVIDIA Tegra X1 platform.We propose a modification of the MemGuard tool to be practically usable on ARM platforms. We also analyse a throttling mechanism of Tegra X1 memory controller, that allows controlling memory bandwidth of non-CPU clients such as the GPU. We show that this mechanism can be used to make the execution time of CPU tasks more predictable. |
Year | Venue | Field |
|---|---|---|
2017 | 2017 IEEE 26TH INTERNATIONAL SYMPOSIUM ON INDUSTRIAL ELECTRONICS (ISIE) | USable,x86,Memory bandwidth,Computer science,Execution model,Multi-core processor,PowerPC,Memory controller,Benchmark (computing),Embedded system |
DocType | ISSN | Citations |
Conference | 2163-5137 | 0 |
PageRank | References | Authors |
0.34 | 7 | 3 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Premysl Houdek | 1 | 0 | 0.34 |
| Michal Sojka | 2 | 9 | 4.13 |
| hanzalek zdeněk | 3 | 101 | 22.42 |