Paper Info
Title
A heterogeneous time-triggered architecture on a hybrid system-on-a-chip platform
Abstract
There is a huge discrepancy between off-the-shelf (COTS) hardware architectures and requirements for embedded industrial applications. Industrial systems are getting more complex by the day, and an interaction of highly diverse components within these systems is unavoidable. An implementation of such systems on COTS hardware is challenging. Platforms based on single-core CPUs is becoming limited, and use of multicore architectures yields safety risks, and overall inefficiency. Tailored architectures provide adequate service but they lack flexibility and therefore their economic justification is limited. Emerging technologies i.e., hybrid system-on-chip combined with novel architectural concepts are filling blind spots between COTS architectures and embedded industrial applications. The paper presents the implementation of an MPSoC architecture on a hybrid system-on-a-chip platform. This architecture provides unique capabilities for embedded applications, in particular, the possibility to host mixed-criticiality and cross-domain applications.
Year
DOI
Venue
2016
10.1109/ISIE.2016.7744897
2016 IEEE 25th International Symposium on Industrial Electronics (ISIE)
Keywords
Field
DocType
heterogeneous time-triggered architecture,hybrid system-on-a-chip platform,off-the-shelf hardware architectures,COTS hardware,embedded industrial applications,single-core CPU,multicore architecture yield safety risks,MPSoC architecture,cross-domain applications,mixed-criticiality applications
Architecture,System on a chip,Field-programmable gate array,Emerging technologies,Engineering,Time-triggered architecture,Multi-core processor,Hybrid system,MPSoC,Embedded system
Conference
ISSN
ISBN
Citations 
2163-5137
978-1-5090-0874-2
0
PageRank 
References 
Authors
0.34
0
2
Name
Order
Citations
PageRank
Haris Isakovic1263.04
Radu Grosu2101197.48