Paper Info
Title
Performance Characterization of Multi-threaded Graph Processing Applications on Many-Integrated-Core Architecture
Abstract
In the age of Big Data, parallel graph processing has been a critical technique to analyze and understand connected data. Meanwhile, Moore's Law continues by integrating more cores into a single chip in the deep-nano regime. Many-Integrated-Core (MIC) processors emerge as a promising solution to process large graphs. In this paper, we empirically evaluate various computing platforms including an Intel Xeon E5 CPU, an Nvidia Tesla P40 GPU and a Xeon Phi 7210 MIC processor codenamed Knights Landing (KNL) in the domain of parallel graph processing. We show that the KNL gains encouraging performance and power efficiency when processing graphs, so that it can become an auspicious alternative to traditional CPUs and GPUs. We further characterize the impact of KNL architectural enhancements on the performance of a state-of-the-art graph framework. We have four key observations: 1 Different graph applications require distinctive numbers of threads to reach the peak performance. For the same application, various datasets need even different numbers of threads to achieve the best performance. 2 Not all graph applications actually benefit from high bandwidth MCDRAMs, while some of them favor low latency DDR4 DRAMs. 3 Vector processing units executing AVX512 SIMD instructions on KNLs are underutilized when running the state-of-the-art graph framework. 4 The sub-NUMA cache clustering mode offering the lowest local memory access latency hurts the performance of graph benchmarks that are lack of NUMA awareness. At last, we suggest future works including system auto-tuning tools and graph framework optimizations to fully exploit the potential of KNL for parallel graph processing.
Year
DOI
Venue
2018
10.1109/ISPASS.2018.00033
2018 IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS)
Keywords
Field
DocType
parallel graph processing,many integrated core architecture,knights landing
Graph theory,Computer architecture,Cache,Computer science,CUDA,Xeon Phi,Parallel computing,SIMD,Xeon,Vector processor,Intel iPSC
Conference
ISBN
Citations 
PageRank 
978-1-5386-5011-0
1
0.34
References 
Authors
36
3
Name
Order
Citations
PageRank
Lei Jiang141.73
Langshi Chen220.69
Judy Qiu332.07