Paper Info
Title
A 3.125-to-28.125 Gb/s multi-standard transceiver with a fully channel-independent operation in 40nm CMOS
Abstract
This paper presents a 3.125 Gb/s to 28.125 Gb/s multi-standard channel-independent parallel transceiver. The proposed clock and data recovery (CDR) IC achieves wide tuning range with low clock jitter because a ring oscillator in each channel is injection-locked to an LC VCO in a global clock generator. Each CDR lane generates a channel-independent injection clock signal using a variable clock divider and a highly linear phase rotator. In addition, a frequency tracking loop using a natural frequency detector is proposed to align the frequency of an injection-locked oscillator to the input data rate to suppress a periodic spur under injection. The test chip fabricated in 40nm CMOS achieves a power efficiency of 4.72 mW/Gb/s while generating integrated jitter of 976 ps <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">rms</sub> .
Year
DOI
Venue
2018
10.1109/CICC.2018.8357073
2018 IEEE Custom Integrated Circuits Conference (CICC)
Keywords
Field
DocType
Clock and data recovery,injection-locked loop,multi-standard transceiver,channel-independent operation,harmonic distortion compensator,frequency tracking loop,natural frequency detector
Clock signal,Linear phase,Clock generator,Ring oscillator,Frequency divider,Computer science,CMOS,Electronic engineering,Voltage-controlled oscillator,Jitter
Conference
ISBN
Citations 
PageRank 
978-1-5386-2484-5
0
0.34
References 
Authors
3
3
Name
Order
Citations
PageRank
Jong-Hyeok Yoon1184.06
Kyeongha Kwon222.08
Hyeon-min Bae39120.77