Name
Title | ||
|---|---|---|
9.1x Error acceptable adaptive artificial neural network coupled LDPC ECC for charge-trap and floating-gate 3D-NAND flash memories |
Abstract | ||
|---|---|---|
Adaptive Artificial Neural Network coupled (ANN) LDPC ECC (ANN-LDPC ECC) is proposed to increase acceptable errors by 9.1-times and to extend the data-retention lifetime by 76-times for charge-trap and floating-gate 3D-NAND flash memories. Adaptive ANN automatically compensates for complex memory cell errors such as lateral charge migration, vertical charge de-trap, inter floating-gate capacitive coupling noise and inter word-line variations. In addition, proposed ANN-LDPC can reproduce the dynamic endurance and data-retention time dependence of errors. Proposed ANN-LDPC is implemented in the storage controller and can precisely and adaptively estimate BER. As a result, memory cell errors are corrected without read time penalty or storage controller size increase. |
Year | DOI | Venue |
|---|---|---|
2018 | 10.1109/CICC.2018.8357064 | 2018 IEEE Custom Integrated Circuits Conference (CICC) |
Keywords | Field | DocType |
3D-TLC NAND flash memory,artificial neural network,LDPC ECC,storage | Control theory,Low-density parity-check code,Computer science,NAND gate,Electronic engineering,Size increase,Artificial neural network,Capacitive coupling,Memory cell | Conference |
ISBN | Citations | PageRank |
978-1-5386-2484-5 | 0 | 0.34 |
References | Authors | |
1 | 3 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Toshiki Nakamura | 1 | 7 | 3.41 |
| Yoshiaki Deguchi | 2 | 2 | 1.86 |
| K. Takeuchi | 3 | 70 | 29.78 |