Name
Abstract | ||
|---|---|---|
This paper presents the characterization of network delays in an IEC61850 process bus substation area network, both through theoretical analysis and simulations. Several design targets were defined considering the recommendations of standards and good design practices: number of network hops, total network delay, probability of the delay being exceeded, link load, network topology and availability... |
Year | DOI | Venue |
|---|---|---|
2018 | 10.1109/TII.2017.2731618 | IEEE Transactions on Industrial Informatics |
Keywords | Field | DocType |
Delays,Substations,Network topology,Topology,Object oriented modeling,IEC Standards,Analytical models | Network delay,Bus network,Computer science,Network architecture,Network simulation,Network topology,Real-time computing,Cumulative distribution function,Network traffic simulation,Processing delay | Journal |
Volume | Issue | ISSN |
14 | 5 | 1551-3203 |
Citations | PageRank | References |
1 | 0.63 | 0 |
Authors | ||
9 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| André Moraes dos Santos | 1 | 53 | 11.17 |
| Bruno Soares | 2 | 1 | 0.63 |
| Chen Fan | 3 | 3 | 2.67 |
| Martijn Kuipers | 4 | 6 | 1.80 |
| Sérgio Sabino | 5 | 1 | 1.64 |
| António Grilo | 6 | 193 | 26.28 |
| Paulo Rogério Pereira | 7 | 137 | 12.71 |
| Mário Serafim Nunes | 8 | 46 | 11.24 |
| Augusto Casaca | 9 | 133 | 32.50 |