Paper Info
Title
Leveraging Hardware Transactional Memory for Cache Side-Channel Defenses.
Abstract
A program's use of CPU caches may reveal its memory access pattern and thus leak sensitive information when the program performs secret-dependent memory accesses. In recent studies, it has been demonstrated that cache side-channel attacks that extract secrets by observing the victim program's cache uses can be conducted under a variety of scenarios, among which the most concerning are cross-VM attacks and those against SGX enclaves. In this paper, we propose a mechanism that leverages hardware transactional memory (HTM) to enable software programs to defend themselves against various cache side-channel attacks. We observe that when the HTM is implemented by retrofitting cache coherence protocols, as is the case of Intel's Transactional Synchronization Extensions, the cache interference that is necessary in cache side-channel attacks will inevitably terminate hardware transactions. We provide a systematic analysis of the security requirements that a software-only solution must meet to defeat cache attacks, propose a software design that leverages HTM to satisfy these requirements and devise several optimization techniques in our implementation to reduce performance impact caused by transaction aborts. The empirical evaluation suggests that the performance overhead caused by the HTM-based solution is low.
Year
DOI
Venue
2018
10.1145/3196494.3196501
AsiaCCS
Field
DocType
ISBN
Software design,Computer security,Cache,Computer science,CPU cache,Transactional Synchronization Extensions,Transactional memory,Side channel attack,Information sensitivity,Operating system,Cache coherence
Conference
978-1-4503-5576-6
Citations 
PageRank 
References 
4
0.37
8
Authors
7
Name
Order
Citations
PageRank
Sanchuan Chen142.40
Fangfei Liu233612.31
Zeyu Mi3123.19
Yinqian Zhang494548.00
Ruby Lee52460261.28
Haibo Chen61749123.40
Xiao-Feng Wang7354.78