Name
Abstract | ||
|---|---|---|
Transaction memory (TM) is a programming friendly technology for thread synchronization in parallel programming paradigm. Transaction memory maintains Atomicity, Consistency, Isolation and Durability (ACID) characters of transactions. When data conflicts in multi-thread paradigm, the transaction has to be aborted, rolled back, and executed again and again until the transaction commits successfully. Although such infinitely retrying strategy of TM has only one exit and the programming flow of applications is very simple, its parallel efficiency is not high enough. In this paper, we proposed a new transaction memory model for parallel programming. When the transaction aborts N times for the reason of data conflict, we will append this transaction to the tail of task queue. We implement this N-retry TM model in software and hardware transaction memory platform. The experimental results show that the proposed TM model can reduce 40% of transaction aborts, and improve the parallel performance 25% on software TM platform and 11% on hardware TM platform. |
Year | DOI | Venue |
|---|---|---|
2017 | 10.1109/ISPA/IUCC.2017.00124 | 2017 15TH IEEE INTERNATIONAL SYMPOSIUM ON PARALLEL AND DISTRIBUTED PROCESSING WITH APPLICATIONS AND 2017 16TH IEEE INTERNATIONAL CONFERENCE ON UBIQUITOUS COMPUTING AND COMMUNICATIONS (ISPA/IUCC 2017) |
Keywords | Field | DocType |
multi-thread programming, transaction memory, intel Transactional Synchronization Extensions (TSX), transactional locking 2 | Instruction set,Computer science,Transactional memory,Thread (computing),Human–computer interaction,Append,Software,Memory model,Synchronization (computer science),Database transaction,Operating system | Conference |
ISSN | Citations | PageRank |
2158-9178 | 0 | 0.34 |
References | Authors | |
0 | 5 | |