Name
Abstract | ||
|---|---|---|
This paper presents an efficient architecture of number Theoretical transform (NTT), targeting at fulfilling large integer multiplication for fully homomorphic encryption applications. A systematic memory management scheme is proposed for the pipelined shared-memory NTT architecture implemented with mixed-radix multi-path delay commutators (MDCs). The presented data relocation scheme along with the MDC can be applied to merge multiple banks with single-port memory for further reducing the area requirement. Experimental results show that a 1,179,648-bit multiplier implemented by the proposed solution, including seamless data transfer among the building blocks, can lead to more than 39.8% area reduction with even a lower computational time as compared with the related works. |
Year | DOI | Venue |
|---|---|---|
2018 | 10.1109/VLSI-DAT.2018.8373254 | 2018 International Symposium on VLSI Design, Automation and Test (VLSI-DAT) |
Keywords | Field | DocType |
high-performance NTT architecture,integer multiplication,fully homomorphic encryption applications,systematic memory management scheme,pipelined shared-memory NTT architecture,mixed-radix multipath delay commutators,multiple banks,single-port memory,seamless data transfer,data relocation scheme,1,179,648-bit multiplier | Homomorphic encryption,Integer multiplication,Architecture,Data transmission,Computer science,Convolution,Parallel computing,Electronic engineering,Multiplier (economics),Memory management,Merge (version control) | Conference |
ISSN | ISBN | Citations |
2474-2724 | 978-1-5386-4261-0 | 0 |
PageRank | References | Authors |
0.34 | 9 | 2 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Jheng-Hao Ye | 1 | 15 | 3.05 |
| Ming-Der Shieh | 2 | 29 | 11.02 |