Name
Abstract | ||
|---|---|---|
This paper presents an implementation of an energy efficient bit-plane payload design for machine learning processor. The proposed architecture facilitates high parallelism and high data bandwidth and thus improves the model learning/training time of machine learning algorithms. By assembling multiple bits as a bit-plane and enlarging query parallelism with a central compare-flag updater, data processing parallelism can be increased. Binary sequential partition (BSP), a fast density estimation algorithm capable of dealing with high dimensional data sets, is realized. Fabricated in 90nm 1P9M CMOS process, the processing rate can achieve 16.9 Gb/sec with 8 queries for data dimension D=210. The test chip integrates 64 counting cells and provides 5 modes with power consumptions of 1.86mJ/Gb per Query. |
Year | DOI | Venue |
|---|---|---|
2018 | 10.1109/VLSI-DAT.2018.8373265 | 2018 International Symposium on VLSI Design, Automation and Test (VLSI-DAT) |
Keywords | Field | DocType |
big data analysis,bit-plane,hardware architecture,Bayesian sequential partition | Data modeling,Data processing,Bit plane,Computer science,Chip,CMOS,Bandwidth (signal processing),Artificial intelligence,Machine learning,Hardware architecture,Payload | Conference |
ISSN | ISBN | Citations |
2474-2724 | 978-1-5386-4261-0 | 0 |
PageRank | References | Authors |
0.34 | 1 | 6 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Fang-Ju Ku | 1 | 0 | 0.34 |
| Tung-Yu Wu | 2 | 27 | 5.23 |
| Yen-chin Liao | 3 | 69 | 8.85 |
| Hsie-Chia Chang | 4 | 474 | 49.13 |
| Wing Hung Wong | 5 | 607 | 96.45 |
| Chen-Yi Lee | 6 | 1211 | 152.40 |