Paper Info
Title
RVNoC: A Framework for Generating RISC-V NoC-Based MPSoC.
Abstract
With the increase in the number of cores embedded on a chip; The main challenge for Multiprocessor System-on-Chip (MPSoC) platforms is the interconnection between that massive number of cores. Networks-on-Chip (NoC) was introduced to solve that challenge, by providing a scalable and modular solution for communication between the cores. In this paper, we introduce a configurable MPSoC framework called RVNoC that generates synthesizable RTL that can be used in both ASIC and FPGA implementations. The proposed framework is based on the open source RISC-V Instruction Set Architecture (ISA) and an open source configurable flit-based router for interconnection between cores, with a core network interface of our design to connect each core with its designated router. A benchmarking environment is developed to evaluate variant parameters of the generated MPSoC. Synthesis of a single building block containing a single core without any peripherals, a router, and a core network interface, using 45nm technology, shows an area of 102.34 kilo Gate Equivalents (kGE), a maximum frequency of 250 MHz, and a 9.9 mu W/MHz power consumption.
Year
DOI
Venue
2018
10.1109/PDP2018.2018.00103
Euromicro Conference on Parallel Distributed and Network-Based Processing
Keywords
Field
DocType
Multiprocessor System-on-Chip (MPSoC),Network-on-Chip (NoC),RISC-V,System-on-Chip (SoC)
RISC-V,Single-core,Computer science,Core network,Instruction set,Parallel computing,Application-specific integrated circuit,Router,Interconnection,MPSoC,Embedded system
Conference
ISSN
Citations 
PageRank 
1066-6192
0
0.34
References 
Authors
0
8
Name
Order
Citations
PageRank
Mahmoud A. Elmohr100.34
Ahmed S. Eissa200.34
Moamen Ibrahim300.34
Mostafa Khamis400.68
Sameh El-Ashry500.34
Ahmed Shalaby600.68
Mohamed Abdelsalam774.85
M. Watheq El-Kharashi815931.92