Name
Abstract | ||
|---|---|---|
A 1-V 23-mu W Sigma-Delta ADC for high-accuracy and low-power applications is presented in a standard 0.18-mu m CMOS technology. To achieve high accuracy with low power consumption in low voltage environment, the proposed modulator is implemented with a 1-bit 3rd-order topology, in which the input-feedforward structure and switched-opamp technique are combined. Meanwhile, a pseudo RAM architecture is proposed for the decimation filter. The ADC achieves 88-dB DR over a 300-Hz bandwidth with an OSR of 128, while it consumes 23 mu W and occupies 0.69mm(2). |
Year | Venue | Field |
|---|---|---|
2015 | PROCEEDINGS OF 2015 IEEE 11TH INTERNATIONAL CONFERENCE ON ASIC (ASICON) | Decimation,Computer science,Modulation,Electronic engineering,Delta-sigma modulation,CMOS,Bandwidth (signal processing),Low voltage,Electrical engineering,Power consumption |
DocType | ISSN | Citations |
Conference | 2162-7541 | 0 |
PageRank | References | Authors |
0.34 | 0 | 5 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Long Zhao | 1 | 0 | 4.06 |
| Chenxi Deng | 2 | 0 | 1.01 |
| Hongming Chen | 3 | 13 | 1.77 |
| Guan Wang | 4 | 16 | 5.17 |
| Yu-Hua Cheng | 5 | 2 | 5.85 |