Name
Abstract | ||
|---|---|---|
Power consumption becomes issue in circuit design, and low voltage design is a good candidate for low power. However, the timing variation becomes greater when supply voltage scales down to near-threshold resign. The existing methods could not work well at low voltage. We propose a new clock buffer which can get low variation at near-threshold. Our proposal reduces the variation from 139% to 30.3% of 7 level buffer compared to normal buffer, at 0.4V, 32/28nm technology. |
Year | Venue | Keywords |
|---|---|---|
2015 | PROCEEDINGS OF 2015 IEEE 11TH INTERNATIONAL CONFERENCE ON ASIC (ASICON) | Low power, variation reduction, clock buffer, adaptive delay |
Field | DocType | ISSN |
Computer science,Voltage,Clock buffer,Circuit design,Electronic engineering,Real-time computing,Low voltage,Power consumption | Conference | 2162-7541 |
Citations | PageRank | References |
0 | 0.34 | 0 |
Authors | ||
2 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Yafei Liu | 1 | 0 | 0.34 |
| Xiangyu Li | 2 | 27 | 10.25 |