Name
Abstract | ||
|---|---|---|
A low-cost SoC implementation of AES algorithm for bio-signals is proposed in this paper. In order to reduce signal delay, we propose three kinds of structure, namely the classic architecture, the architecture including a DMA and the architecture with the wavelet transform module and AES module integrated. As a result, the architecture with modules integrated can obtain minimum data latency and minimum area. In this design, we present a simplified 5/3 lifting wavelet processor (LWP) and a compact AES algorithm hardware accelerator (AESACR) for the purpose of reducing the area of the SoC. In SMIC 65nm CMOS process, the area of the optimal structure is 48813um(2). Meanwhile, the maximum throughput is 633Mbps and the maximum frequency reaches 1GHz. |
Year | Venue | Field |
|---|---|---|
2015 | PROCEEDINGS OF 2015 IEEE 11TH INTERNATIONAL CONFERENCE ON ASIC (ASICON) | Architecture,Computer science,Algorithm,Cmos process,Real-time computing,Hardware acceleration,Throughput,Signal delay,Data latency,Wavelet transform,Wavelet,Embedded system |
DocType | ISSN | Citations |
Conference | 2162-7541 | 0 |
PageRank | References | Authors |
0.34 | 0 | 5 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Zhicheng Xie | 1 | 0 | 0.68 |
| Jun Han | 2 | 91 | 24.48 |
| Jianwei Yang | 3 | 58 | 12.73 |
| lijun zhou | 4 | 0 | 4.39 |
| Xiaoyang Zeng | 5 | 442 | 107.26 |