Paper Info
Title
A 6bit 4gs/S Current-Steering Digital-To-Analog Converter In 40nm Cmos With Adjustable Bias And Dft Block
Abstract
In this paper, a 6-bit high-speed digital-to-analog converter (DAC) is presented. This DAC is based on a segmented architecture and has an operating speed up to 4GS/s according to the post-layout simulation results. The output waveform of this DAC is realized in a non-return-to-zero (NRZ) way. The DAC core occupies an area of 0.09mm(2) in a 40nm CMOS technology. A DfT block is introduced to relieve the speed requirement of high-speed I/O. The spurious free dynamic range (SFDR) up to 44.81dBc is achieved over Nyquist interval. The power consumption is 13mW at near Nyquist frequency.
Year
Venue
Field
2015
PROCEEDINGS OF 2015 IEEE 11TH INTERNATIONAL CONFERENCE ON ASIC (ASICON)
Integral nonlinearity,Nyquist frequency,Computer science,Operating speed,Waveform,Spurious-free dynamic range,Electronic engineering,CMOS,Digital-to-analog converter,Electrical engineering,Nyquist rate
DocType
ISSN
Citations 
Conference
2162-7541
0
PageRank 
References 
Authors
0.34
0
3
Name
Order
Citations
PageRank
Long Zhao104.06
Ji He200.34
Yu-Hua Cheng325.85