Name
Abstract | ||
|---|---|---|
With the improvement of chip integration, influence of substrate coupling noise to sensitive circuits increases. Considering the effect of substrate noise advanced is necessary for circuit and layout designing. Based on previous work, this paper utilized a 3D distributed RC substrate model and power/ground model. A model of noise source caused by digital circuits switching of the whole mixed-signal chip is developed. And the impact of substrate coupling noise on CDR is discussed through quantitative analysis. Finally, effective measures are applied to suppression the sub-noise, such as physical distance isolation and guard-ring (GR) isolation. Compared with physical isolation, the GR can suppress the sub-noise more effectively. Meanwhile, the region of GR should be selected to get the strongest effect and optimize the circuit performance. |
Year | DOI | Venue |
|---|---|---|
2015 | 10.1109/ASICON.2015.7516920 | 2015 IEEE 11th International Conference on ASIC (ASICON) |
Keywords | Field | DocType |
clock and data recovery,guard-ring isolation,physical distance isolation,CDR,mixed-signal chip,digital circuits switching,noise source,power-ground model,3D distributed RC substrate model,substrate coupling noise,chip integration | Substrate (chemistry),Digital electronics,Computer science,Substrate coupling,Chip,Electronic engineering,Data recovery,Circuit performance,Electronic circuit,Electrical engineering | Conference |
ISSN | ISBN | Citations |
2162-7541 | 978-1-4799-8486-2 | 0 |
PageRank | References | Authors |
0.34 | 0 | 6 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Yongsheng Wang | 1 | 0 | 2.03 |
| Min Wang | 2 | 169 | 36.41 |
| Huaixin Xian | 3 | 0 | 0.34 |
| Yunfei Du | 4 | 72 | 14.62 |
| Bei Cao | 5 | 0 | 0.68 |
| Xiaowei Liu | 6 | 7 | 6.98 |