Paper Info
Title
Design Of A High Parallelism High Throughput Hspa Plus Turbo Decoder
Abstract
Research in high throughput, high performance Turbo coding systems has an important significance for the development of modern wireless communication systems. This work presents a design of a high parallelism high throughput HSPA+ Turbo decoder in which a novel anti-contention structure named TMFDB is adopted to solve the memory contention problem more efficiently. The circuit is synthesized by Synopsys DC with TSMC LP 65nm technology, and the result shows that it can work in a maximum frequency of 465MHz, which means an throughput up to 792Mbps when the number of iteration is set to 5.5, and meet HSPA+'s throughput demands of 672Mbps.
Year
DOI
Venue
2015
10.1109/ASICON.2015.7517198
PROCEEDINGS OF 2015 IEEE 11TH INTERNATIONAL CONFERENCE ON ASIC (ASICON)
Field
DocType
ISSN
Wireless communication systems,Computer science,Turbo code,Turbo decoder,Real-time computing,Throughput
Conference
2162-7541
Citations 
PageRank 
References 
0
0.34
0
Authors
3
Name
Order
Citations
PageRank
Jieqiong Cheng100.68
Qingqing Yang271.68
Xiaofang Zhou3114.11