Name
Abstract | ||
|---|---|---|
Physical Unclonable Functions (PUFs) is increasingly used for IC authentication to protect against cloning, imitating and counterfeiting circuit, which exploits the uncontrollable randomness due to manufacturing process variations to generate low cost secret keys. But it meets threaten by numerical modeling attacks. In the paper, a power-up and arbiter hybrid PUFs is proposed to resistant modeling attacks and is designed in TSMC 65nm CMOS technology. The hybrid PUFs integrated the advantages of the two types PUFs circuits. In the form of custom designed, the 256-bit hybrid PUFs occupies about 115 mu m x 116 mu m. Experimental results show that the hybrid PUFs have reliability and randomness. |
Year | Venue | Field |
|---|---|---|
2015 | PROCEEDINGS OF 2015 IEEE 11TH INTERNATIONAL CONFERENCE ON ASIC (ASICON) | Arbiter,Authentication,Computer science,Electronic engineering,CMOS,Physical unclonable function,Electronic circuit,Numerical modeling,Manufacturing process,Randomness,Embedded system |
DocType | ISSN | Citations |
Conference | 2162-7541 | 0 |
PageRank | References | Authors |
0.34 | 0 | 5 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Yuejun Zhang | 1 | 0 | 1.35 |
| Pengjun Wang | 2 | 62 | 11.93 |
| Gang Li | 3 | 421 | 79.69 |
| Haoyu Qian | 4 | 0 | 0.34 |
| Xiaomin Zheng | 5 | 0 | 0.34 |