Name
Abstract | ||
|---|---|---|
In this paper, we propose an ultra-short length stochastic computation (SC) method based on multiple partition computing (MPC). For example, in MPC four parallel 16-bits streams can represent a 16-bits fixed-point number, while a 65536-bits stream is required in traditional SC. To achieve this, MPC partitions a fixed-point number to several short parts and converts each part to a short stream separately. A high performance stochastic multiplier and a divider are also proposed based on MPC. As a case study, we implement a 4×4 matrix multiplication with field programmable gate array (FPGA). The synthesis reports shows that the hardware efficiency of the proposed method is 76X times more than traditional SC and 23% improvement than the traditional fixed-point computation. |
Year | DOI | Venue |
|---|---|---|
2015 | 10.1109/ASICON.2015.7516930 | 2015 IEEE 11th International Conference on ASIC (ASICON) |
Keywords | Field | DocType |
Stochastic Computation (SC),Multiple Partition Computing (MPC),ultra-short length | Computer science,Field-programmable gate array,Electronic engineering,Multiplier (economics),Real-time computing,Partition (number theory),Matrix multiplication,Computation | Conference |
ISSN | ISBN | Citations |
2162-7541 | 978-1-4799-8486-2 | 0 |
PageRank | References | Authors |
0.34 | 0 | 3 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Jienan Chen | 1 | 17 | 8.93 |
| Hu Jianhao | 2 | 96 | 20.56 |
| Jiangyun Zhou | 3 | 5 | 1.83 |