Paper Info
Title
QoSinNoC: Analysis of QoS-Aware NoC Architectures for Mixed-Criticality Applications
Abstract
Multi-Processor Systems-on-Chip (MPSoCs) have been a clear new trend in processor-based systems design. General purpose MPSoC designers have turned to the Network-on-Chip (NoC) interconnect model to surpass the limitations imposed by traditional bus- or crossbar-based interconnection. This technology is also a promising solution for safety-critical industries where, primarily due to power and weight constraints, there is an increasing need in embedded systems for implementing multiple functionalities upon a single shared computing platform. This paper proposes a QoSinNoC framework, which is based on a set of quality of service (QoS) aware NoC architectures along with the analysis methodology including selected relevant metrics that enable an efficient trade-off between guarantees and overheads in mixed-criticality application scenarios. QoSinNoC architectures overcome the notion of strictly divided regions by allowing non-critical communication pass through the critical region, providing they do not utilize common router resources. This work aims to facilitate the usage of NoC technology by safety-critical industries such as avionics.
Year
DOI
Venue
2018
10.1109/DDECS.2018.00-10
2018 IEEE 21st International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS)
Keywords
Field
DocType
mixed-criticality applications,network-on-chip,quality-of-service
Computer science,Avionics,Network on a chip,Systems design,Mixed criticality,Quality of service,Real-time computing,Router,MPSoC,Crossbar switch,Distributed computing
Conference
ISBN
Citations 
PageRank 
978-1-5386-5755-3
0
0.34
References 
Authors
9
7
Name
Order
Citations
PageRank
Serhiy Avramenko162.31
Siavoosh Payandeh Azad2116.94
Stefano Esposito3213.34
Behrad Niazmand4225.76
Massimo Violante560266.91
Jaan Raik621151.77
Maksim Jenihhin77025.02