Paper Info
Title
A high IIP3 6.5 mW self-biased 0.3–3 GHz small area LNA
Abstract
This paper presents a 300 MHz to 3 GHz Low-Noise Amplifier (LNA) with high HP3 and one of the smallest silicon area we could find. It is based on a single amplifier, where it is systematically optimized to achieve better results than more complex noise canceling topologies, thus, saving area and power consumption. A CMOS inverter with resistive feedback where transistors are self-biased in strong inversion is designed and optimized for low NF and high IIP3 and then the feedback resistor is calculated for input impedance matching. The post-layout simulation results in a 130 nm process show for the entire bandwidth a voltage gain around 12 to 15 dB, a NF <; 3.6 dB, a Sii of -15.2 to -10.5 dB, HP3 of 4.7 to 5.3 dBm, total area of 40 um × 30 um and power consumption of 6.5 mW under 1.2 V supply. Monte Carlo simulations for 1000 samples show IIP3 of 3.3 to 6 dBm with σ of 0.48 dBm.
Year
DOI
Venue
2017
10.1109/LASCAS.2017.7948086
2017 IEEE 8th Latin American Symposium on Circuits & Systems (LASCAS)
Keywords
Field
DocType
self-biased small-area LNA,low-noise amplifier,silicon area,noise canceling topology,power consumption,CMOS inverter,resistive feedback,feedback resistor,input impedance matching,post-layout simulation,voltage gain,Monte Carlo simulation,frequency 0.3 GHz to 3 GHz,power 6.5 mW,size 130 nm,voltage 1.2 V
Inverter,Noise measurement,Computer science,Voltage,Electronic engineering,Bandwidth (signal processing),Resistor,Input impedance,Transistor,Electrical engineering,Amplifier
Conference
ISBN
Citations 
PageRank 
978-1-5090-5860-0
0
0.34
References 
Authors
7
3
Name
Order
Citations
PageRank
Arthur Liraneto Torres Costa162.38
hamilton klimach27120.07
Sergio Bampi3184.10