Name
Abstract | ||
|---|---|---|
Static Random Access Memory (SRAM)-based routing multiplexers, whatever structure is employed, share a common limitation: their area, delay and power increase linearly with the input size. This property results in most SRAM-based FPGA architectures typically avoiding the use of large multiplexers. Resistive Random Access Memory (RRAM)-based multiplexers, built with one-level structure, have a unique advantage over SRAM-based multiplexers: their ideal delay is independent from the input size. This property allows RRAM-based FPGA architectures to use larger multiplexers than their SRAM-based counterparts, without generating any delay overhead. In this paper, by carefully considering the properties of RRAM multiplexers, we assess that current state-of-art architectural parameters for SRAM-based FPGAs cannot preserve optimality in the context of RRAM-based FPGAs. As a result, we propose that in RRAM-based FPGAs, (a) the routing tracks should be interconnected to Look-Up Table (LUT) inputs via a one-level crossbar, instead of through Connection Blocks and local routing; (b) the Switch Blocks should employ larger multiplexers; (c) length-2 wires should be used instead of length-4 wires. When operated in nominal voltage, the proposed RRAM-based FPGA architecture reduces area by 26%, delay by 39% and channel width by 13%, as compared to a SRAM-based FPGA with a classical architecture. When operated in the near-V
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regime, the proposed RRAM-based FPGA architecture improves Area-Delay Product by 42% and Power-Delay Product by 5× as compared to a classical SRAM-based FPGA at nominal voltage. |
Year | DOI | Venue |
|---|---|---|
2017 | 10.1109/LASCAS.2017.7948107 | 2017 IEEE 8th Latin American Symposium on Circuits & Systems (LASCAS) |
Keywords | Field | DocType |
power-delay product,area-delay product,wire,switch block,connection block,one-level crossbar,LUT,look-up table,RRAM multiplexer,resistive random access memory,FPGA architecture,routing multiplexer,SRAM,static random access memory,optimization | Lookup table,Computer science,Voltage,Field-programmable gate array,Electronic engineering,Multiplexer,Static random-access memory,Multiplexing,Crossbar switch,Resistive random-access memory | Conference |
ISBN | Citations | PageRank |
978-1-5090-5860-0 | 0 | 0.34 |
References | Authors | |
6 | 3 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Xifan Tang | 1 | 59 | 12.89 |
| Giovanni De Micheli | 2 | 10245 | 1018.13 |
| Pierre-Emmanuel Gaillardon | 3 | 355 | 55.32 |