Title
CMOS analog multiplier with high rejection of power supply ripple
Abstract
This work proposes a new architecture of a CMOS analog multiplier based on transistors operating in nonsaturation region, from weak to strong inversion, featuring low sensitivity to voltage supply variations. In addition, the multiplier shows desirable characteristics for the compact implementation of Cellular Neural Networks, namely both voltage and current inputs, current output, and modularity. Simulation results have demonstrated low power consumption and low sensitivity to supply voltage.
Year
DOI
Venue
2018
10.1109/LASCAS.2018.8399976
2018 IEEE 9th Latin American Symposium on Circuits & Systems (LASCAS)
Keywords
Field
DocType
CMOS Analog Multiplier,Synapse,CNN
Analog multiplier,Computer science,Voltage,Electronic engineering,CMOS,Multiplier (economics),Transistor,Ripple,Cellular neural network,Modularity
Conference
ISSN
ISBN
Citations 
2330-9954
978-1-5386-2312-1
1
PageRank 
References 
Authors
0.48
0
3