Paper Info
Title
Modular Routing Design for Chiplet-Based Systems.
Abstract
System-on-Chip (SoC) complexity and the increasing costs of silicon motivate the breaking of an SoC into smaller "chiplets." A chiplet-based SoC design process has the promise to enable fast SoC construction by using advanced packaging technologies to tightly integrate multiple disparate chips (e.g., CPU, GPU, memory, FPGA). However, when assembling chiplets into a single SoC, correctness validation becomes a significant challenge. In particular, the network-on-chip (NoC) used within the individual chiplets and across chiplets to tie them together can easily have deadlocks, especially if each chip is designed in isolation. We introduce a simple, modular, yet elegant methodology for ensuring deadlock-free routing in multi-chiplet systems. As an example, we focus on future systems combining chiplets on an active silicon interposer. To maximize modularity, each individual chiplet is free to implement its own NoC topology and local routing algorithm, and the interposer can implement its own independent topology and routing. Our methodology imposes a few simple turn restrictions applied only to traffic as it flows into or out of the chiplets from the interposer, and we provide a way to determine these restrictions. The end result is an overall approach that enables highly-modular, chiplet-based SoC construction while eliminating deadlocks with high performance.
Year
DOI
Venue
2018
10.1109/ISCA.2018.00066
ISCA
Keywords
Field
DocType
chiplet, deadlock-avoidance, routing
Computer science,Deadlock,Correctness,Parallel computing,Field-programmable gate array,Chip,Interposer,Modular design,Design process,Modularity,Embedded system
Conference
ISSN
ISBN
Citations 
1063-6897
978-1-5386-5984-7
3
PageRank 
References 
Authors
0.41
30
7
Name
Order
Citations
PageRank
Jieming Yin1434.72
Zhifeng Lin2106.30
Onur Kayıran335613.47
Matthew Poremba4785.46
Muhammad Shoaib Bin Altaf530.41
Natalie Enright Jerger6126856.57
Gabriel H. Loh7121.85