Name
Title | ||
|---|---|---|
Stitch: Fusible Heterogeneous Accelerators Enmeshed with Many-Core Architecture for Wearables. |
Abstract | ||
|---|---|---|
Wearable devices are now leveraging multi-core processors to cater to the increasing computational demands of the applications via multi-threading. However, the power, performance constraints of many wearable applications can only be satisfied when the thread-level parallelism is coupled with hardware acceleration of common computational kernels. The ASIC accelerators with high performance/watt suffer from high non-recurring engineering costs. Configurable accelerators that can be reused across applications present a promising alternative. Autonomous configurable accelerators loosely-coupled to the processor occupy additional silicon area for local data and control and incur data communication overhead. In contrast, configurable instruction set extension (ISE) accelerators tightly integrated into the processor pipeline eliminate such overheads by sharing the existing processor resources. Yet, naively adding full-blown ISE accelerators to each core in a many-core architecture will lead to huge area and power overheads, which is clearly infeasible in resource-constrained wearables. In this paper, we propose Stitch, a many-core architecture where tiny, heterogeneous, configurable and fusible ISE accelerators, called polymorphic patches are effectively enmeshed with the cores. The novelty of our architecture lies in the ability to stitch together multiple polymorphic patches, where each can handle very simple ISEs, across the chip to create large, virtual accelerators that can execute complex ISEs. The virtual connections are realized efficiently with a very lightweight compiler-scheduled network-on-chip (NoC) with no buffers or control logic. Our evaluations across representative wearable applications show an average 2.3X improvement in runtime for Stitch compared to a baseline many-core processor without ISEs, at a modest area and power overhead.
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Year | DOI | Venue |
|---|---|---|
2018 | 10.1109/ISCA.2018.00054 | ISCA |
Keywords | Field | DocType |
Manycore architectures, accelerators, low-power, customization, network-on-chip, wearables | Yarn,Wearable computer,Instruction set,Computer science,Parallel computing,Network on a chip,Application-specific integrated circuit,Hardware acceleration,Control logic,Wearable technology,Embedded system | Conference |
ISSN | ISBN | Citations |
1063-6897 | 978-1-5386-5984-7 | 2 |
PageRank | References | Authors |
0.35 | 41 | 4 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Cheng Tan | 1 | 38 | 9.50 |
| Manupa Karunaratne | 2 | 19 | 2.02 |
| Tulika Mitra | 3 | 2714 | 135.99 |
| Li-Shiuan Peh | 4 | 5077 | 398.57 |