Paper Info
Title
A 5.16Gbps decoder ASIC for Polar Code in 16nm FinFET
Abstract
Polar codes has been selected as 5G standard. However, only a couple of ASIC featuring decoders are fabricated, and none of them support list size L > 4 and code length N > 1024. This paper presents an ASIC implementation of three decoders for polar code: successive cancellation (SC) decoder, flexible decoder and ultra-reliable decoder. These decoders are all SC based decoder, supporting list size up to 1,8,32 and code length up to 2 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">15</sup> ,2 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">14</sup> ,2 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">11</sup> respectively. This chip is fabricated in a 16nm TSMC FinFET technology, and can be clocked at 1 Ghz. Optimization techniques are proposed and employed to increase throughput. Experiment result shows that the throughput can achieve up to 5.16Gbps. Compared with fabricated AISC decoder and synthesized decoder in literature, the flexible decoder achieves higher area efficiency.
Year
DOI
Venue
2018
10.1109/ISWCS.2018.8491225
2018 15th International Symposium on Wireless Communication Systems (ISWCS)
Keywords
DocType
Volume
Polar code,ASIC,decoding,SCL
Conference
abs/1807.01451
ISSN
ISBN
Citations 
2154-0217
978-1-5386-5006-6
0
PageRank 
References 
Authors
0.34
9
7
Name
Order
Citations
PageRank
Xiaocheng Liu1735.33
Qifan Zhang264.13
Pengcheng Qiu310.71
Jiajie Tong411.73
Huazi Zhang528924.91
Changyong Zhao600.34
Jun Wang79228736.82