Name
Abstract | ||
|---|---|---|
This article describes the hardware-accelerated implementation of the Twofish encryption algorithm on Field Programmable Gate Array (FPGA) network cards. The encryption core was implemented using the Virtex 7 network card to achieve real-time encryption and decryption. The algorithm was implemented for 128-bit words and 128-bit keys. This article demonstrates that the Twofish encryption core can operate with the maximum clock frequencies of 315 MHz and achieves the throughput of 48 Gbps, which is faster than most currently implemented systems. |
Year | DOI | Venue |
|---|---|---|
2018 | 10.1109/TSP.2018.8441386 | 2018 41st International Conference on Telecommunications and Signal Processing (TSP) |
Keywords | Field | DocType |
Twofish,Encryption,Decryption,Hardware-Accelerated,FPGA,Component,VHDL,Core,Virtex-7 | Computer science,Twofish,Field-programmable gate array,Encryption,Virtex,VHDL,Throughput,Network interface controller,Computer hardware | Conference |
ISBN | Citations | PageRank |
978-1-5386-4696-0 | 0 | 0.34 |
References | Authors | |
0 | 3 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| David Smekal | 1 | 0 | 1.35 |
| Jan Hajny | 2 | 104 | 14.61 |
| Zdenek Martinasek | 3 | 26 | 7.38 |