Name
Abstract | ||
|---|---|---|
The current verification flow of complex systems uses different engines synergistically: virtual prototyping, formal verification, simulation, emulation, and FPGA prototyping. However, none of them is able to verify a complete architecture. On the other hand, hybrid approaches aiming at full verification use techniques that lower the overall complexity by increasing the abstraction level. To bridge this verification gap, we turn to the embedded software and the information it can bring to the verification environment. This work focuses on the semiformal verification of complex systems at the RT level to handle the hardware peculiarities. Our results show an improvement of four times in verification completeness of a complex hardware gateway compared to the commercial tool. |
Year | DOI | Venue |
|---|---|---|
2018 | 10.1109/ISVLSI.2018.00049 | 2018 IEEE Computer Society Annual Symposium on VLSI (ISVLSI) |
Keywords | Field | DocType |
Software driven verification,Semiformal verification,Functional verification,Formal verification,Simulation,Coverage | Embedded software,Computer science,FPGA prototype,Emulation,Default gateway,Software,Abstraction layer,Embedded system,Virtual prototyping,Formal verification | Conference |
ISSN | ISBN | Citations |
2159-3469 | 978-1-5386-7100-9 | 0 |
PageRank | References | Authors |
0.34 | 3 | 3 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Tomas Grimm | 1 | 0 | 0.34 |
| Djones Lettnin | 2 | 39 | 7.68 |
| Hubner, Michael | 3 | 390 | 47.98 |