Name
Abstract | ||
|---|---|---|
Exponential growth of high-end multimedia data processing requirement produces sharply increasing demand on memory capacities of modern computer systems and mobile platforms. As a next generation memory technology, Multi-level Cell Spin-Transfer Torque Random Access Memory (MLC STT-RAM) is a promising candidate for high-performance and high-density applications. However, its multi-bit per cell advantage has been significantly compromised by the redundant memories to overcome the severe reliability concerns. In this paper, we demonstrate that the compressed image data can exhibit very asymmetric error tolerance capabilities across various layers and resolutions. We then propose a reconfigurable high density MLC STT-RAM approximate memory design by leveraging such nature of the compressed data. Our tri-zone design can offer dynamic configuration among half-state, tristate and full-state to satisfy the run-time error requirement without incurring extra error correction overheads. Simulation results show that our design can boost the storage capacity significantly with marginal image quality degradation. |
Year | DOI | Venue |
|---|---|---|
2018 | 10.1109/ISVLSI.2018.00035 | 2018 IEEE Computer Society Annual Symposium on VLSI (ISVLSI) |
Keywords | Field | DocType |
MLC STT RAM,Image compress,Approximate storage | Data processing,Torque,Computer science,Image quality,Error detection and correction,Image resolution,Multimedia,Exponential growth,Random access,Bit error rate | Conference |
ISSN | ISBN | Citations |
2159-3469 | 978-1-5386-7100-9 | 1 |
PageRank | References | Authors |
0.38 | 11 | 5 |