Name
Abstract | ||
|---|---|---|
This paper describes a high-resolution 11.7b Time-to-Digital Converter (TDC) designed in a pure digital CMOS 130nm technology. The target architecture comprises a looped delay-line based on an inverter-based pulse-shrinking technique. The proposed technique can achieve a 0.82ps resolution with a dynamic range of 2.918ns, an integral nonlinearity (INL) of -2.4 to 2.11 and a differential nonlinearity (DNL) of -0.91 to 0.87 LSB. In addition, it occupies a low area of 0.148 mm
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Year | DOI | Venue |
|---|---|---|
2018 | 10.1109/PRIME.2018.8430374 | 2018 14th Conference on Ph.D. Research in Microelectronics and Electronics (PRIME) |
Keywords | Field | DocType |
Time-to-Digital Converter,looped delay-line,inverter-based Pulse-Shrinking technique,high resolution and dynamic-range,low area and power consumption,simple and versatile structure | Integral nonlinearity,Inverter,Dynamic range,Differential nonlinearity,Computer science,Electronic engineering,CMOS,Time-to-digital converter,Least significant bit | Conference |
ISBN | Citations | PageRank |
978-1-5386-5388-3 | 0 | 0.34 |
References | Authors | |
7 | 4 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Rodrigo Granja | 1 | 0 | 0.34 |
| Mauro Santos | 2 | 3 | 1.86 |
| Jorge Guilherme | 3 | 14 | 6.02 |
| Nuno Cavaco Horta | 4 | 310 | 49.65 |