Title | ||
---|---|---|
A 2.7μW/MIPS, 0.88GOPS/mm<sup>2</sup> distributed processor for implantable brain machine interfaces |
Abstract | ||
---|---|---|
This paper presents a scalable architecture in 0.18 μm CMOS for implantable brain machine interfaces (BMI) that enables micro controller flexibility for data analysis at the sensor interface. By introducing more generic computational capabilities the system is capable of high level adaptive function to potentially improve the long term efficacy of invasive implants. This topology features a compact ultra low power distributed processor that supports 64-channel neural recording system on chip (SOC) with a computational efficiency of 2.7 μW/MIPS with a total chip area of 6.2 mm
<sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup>
. This configuration executes 1024 instructions on each core at 20 MHz to consolidate full spectrum high precision recordings from 4 analogue channels for filtering, spike detection, and feature extraction in the digital domain. |
Year | DOI | Venue |
---|---|---|
2016 | 10.1109/BioCAS.2016.7833806 | 2016 IEEE Biomedical Circuits and Systems Conference (BioCAS) |
Keywords | Field | DocType |
feature extraction,spike detection,filtering,neural recording system-on-chip,low power distributed processor,high level adaptive function,sensor interface,data analysis,microcontroller flexibility,CMOS technology,implantable brain machine interfaces | Search engine,System on a chip,Computer science,Communication channel,Filter (signal processing),Feature extraction,CMOS,Chip,Microcontroller,Embedded system | Conference |
ISBN | Citations | PageRank |
978-1-5090-2960-0 | 0 | 0.34 |
References | Authors | |
0 | 2 |
Name | Order | Citations | PageRank |
---|---|---|---|
Lieuwe B. Leene | 1 | 8 | 4.69 |
Timothy G. Constandinou | 2 | 78 | 38.42 |