Name
Abstract | ||
|---|---|---|
A 6-bit 20 GS/s two-channel time-interleaved current-steering digital-to-analog converter (DAC) with compact full-binary sub-DACs is presented. Optimally adjusted transition timings between the input data and the interleaving clock minimize glitches by the time-interleaving switches and enhance the high-frequency linearity. In order to prevent static linearity degradation by the leakage current th... |
Year | DOI | Venue |
|---|---|---|
2018 | 10.1109/TCSII.2018.2809965 | IEEE Transactions on Circuits and Systems II: Express Briefs |
Keywords | Field | DocType |
Clocks,Linearity,Switches,Timing,Leakage currents,Digital-analog conversion,Power demand | Glitch,Logic gate,Circuit complexity,Leakage (electronics),Linearity,CMOS,Electronic engineering,Transistor,Mathematics,Interleaving | Journal |
Volume | Issue | ISSN |
65 | 9 | 1549-7747 |
Citations | PageRank | References |
2 | 0.39 | 0 |
Authors | ||
4 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Si-Nai Kim | 1 | 4 | 0.79 |
| Woo-Cheol Kim | 2 | 37 | 5.46 |
| Min-Jae Seo | 3 | 23 | 4.08 |
| Seung-Tak Ryu | 4 | 299 | 46.61 |