Name
Abstract | ||
|---|---|---|
Due to leakage current, DRAM devices need periodic refresh operations to maintain the validity of data in each DRAM cell. The shorter refresh period is, the more refresh overhead DRAM devices have to amortize. Since the retention time of DRAM cells are different because of process variation, DRAM providers usually set default refresh period as the retention time of those weakest cells that account for less than 0.1% of total capacity. In this paper, we propose DearDRAM (Discard weak rows DRAM), an efficient refresh approach that is able to substantially reduce refresh overhead using two mechanisms: selectively disabling weak rows and remapping their physical addresses to a reserved region. DearDRAM allows DRAM devices to perform refresh operations with a much longer period (increasing from 64ms to 256 ms), which reduces energy consumption. It is worth noting that compared to previous schemes, DearDRAM is easy to be implemented, does not modify DRAM chip and only introduces slight modifications to memory controller. Experimental results show that DearDRAM can save refresh energy an average of 76.12%, save total energy about 12.51% and improve IPC an average of 4.56% in normal temperature mode. |
Year | DOI | Venue |
|---|---|---|
2018 | 10.1007/978-981-13-2423-9_9 | ADVANCED COMPUTER ARCHITECTURE |
Keywords | DocType | Volume |
DRAM,Memory controller,Refresh,Weak cell | Conference | 908 |
ISSN | Citations | PageRank |
1865-0929 | 0 | 0.34 |
References | Authors | |
0 | 3 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Xusheng Zhan | 1 | 0 | 0.68 |
| Yungang Bao | 2 | 361 | 31.11 |
| SUN Ning-Hui | 3 | 1268 | 97.37 |