Name
Abstract | ||
|---|---|---|
Accurate evaluation of Ultra Low Power Systems on Chip (ULP SoC) is a huge challenge for designers and developers. In embedded applications, especially for Internet of Things end-node devices, ULP SoCs have to interact with their environment and need self-management. For this kind of applications, modelling a complete SoC, including processor(s), memories, all the peripherals components, their interaction and low-power policies, can be very complex in terms of developments and benchmarking. In order to cope with this challenge, an approach is to implement the desired system on FPGA with a monitoring infrastructure dedicated to fast and accurate performance evaluation. In this paper, we propose a set of different tools used during the evaluation step that can also be easily implemented on the final product and used by the system itself for self-assessment to enable adaptive behaviour. Illustrated by a simple architecture implemented on an FPGA-based platform, this method brings flexible, cycle accurate, fast and reliable performance evaluation and self-evaluation, with the possibility to use the platform for low-cost prototyping. |
Year | DOI | Venue |
|---|---|---|
2018 | 10.1109/PATMOS.2018.8464173 | 2018 28th International Symposium on Power and Timing Modeling, Optimization and Simulation (PATMOS) |
Keywords | Field | DocType |
FPGA,Cortex-MO,performance evaluation,cycle accurate,self-monitoring | Architecture,Computer science,Internet of Things,Adaptive behaviour,Field-programmable gate array,Electric power system,Embedded applications,Real-time computing,Benchmarking,Embedded system | Conference |
ISSN | ISBN | Citations |
2474-5456 | 978-1-5386-6366-0 | 0 |
PageRank | References | Authors |
0.34 | 3 | 3 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Guillaume Patrigeon | 1 | 4 | 2.52 |
| Pascal Benoit | 2 | 262 | 29.52 |
| Lionel Torres | 3 | 346 | 53.92 |