Title | ||
---|---|---|
TriZone: A Design of MLC STT-RAM Cache for Combined Performance, Energy, and Reliability Optimizations. |
Abstract | ||
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Spin-transfer torque random access memory (STT-RAM) is a promising technology for future nonvolatile caches and memories. To increase the storage density, multilevel cell (MLC) technique was recently introduced to STT-RAM designs at the cost of degraded access speed, reliability, and energy efficiency. Existing MLC STT-RAM cache architectures primarily focus on the performance and energy optimizat... |
Year | DOI | Venue |
---|---|---|
2018 | 10.1109/TCAD.2017.2783860 | IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems |
Keywords | Field | DocType |
Random access memory,Resistance,Magnetic tunneling,Reliability engineering,Computer architecture,Microprocessors | Torque,Efficient energy use,Cache,Computer science,Parallel computing,Real-time computing,Error detection and correction,Operational reliability,Decoding methods,Random access | Journal |
Volume | Issue | ISSN |
37 | 10 | 0278-0070 |
Citations | PageRank | References |
0 | 0.34 | 0 |
Authors | ||
10 |
Name | Order | Citations | PageRank |
---|---|---|---|
Zihao Liu | 1 | 34 | 5.45 |
Mengjie Mao | 2 | 186 | 13.50 |
Tao Liu | 3 | 45 | 7.40 |
Xue Wang | 4 | 18 | 11.66 |
Wujie Wen | 5 | 300 | 30.61 |
Yiran Chen | 6 | 3344 | 259.09 |
Hai Li | 7 | 2435 | 208.37 |
Danghui Wang | 8 | 10 | 3.53 |
Yukui Pei | 9 | 32 | 11.04 |
ning | 10 | 496 | 61.98 |