Title
TriZone: A Design of MLC STT-RAM Cache for Combined Performance, Energy, and Reliability Optimizations.
Abstract
Spin-transfer torque random access memory (STT-RAM) is a promising technology for future nonvolatile caches and memories. To increase the storage density, multilevel cell (MLC) technique was recently introduced to STT-RAM designs at the cost of degraded access speed, reliability, and energy efficiency. Existing MLC STT-RAM cache architectures primarily focus on the performance and energy optimizat...
Year
DOI
Venue
2018
10.1109/TCAD.2017.2783860
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Keywords
Field
DocType
Random access memory,Resistance,Magnetic tunneling,Reliability engineering,Computer architecture,Microprocessors
Torque,Efficient energy use,Cache,Computer science,Parallel computing,Real-time computing,Error detection and correction,Operational reliability,Decoding methods,Random access
Journal
Volume
Issue
ISSN
37
10
0278-0070
Citations 
PageRank 
References 
0
0.34
0
Authors
10
Name
Order
Citations
PageRank
Zihao Liu1345.45
Mengjie Mao218613.50
Tao Liu3457.40
Xue Wang41811.66
Wujie Wen530030.61
Yiran Chen63344259.09
Hai Li72435208.37
Danghui Wang8103.53
Yukui Pei93211.04
ning1049661.98