Title
Fan-in analysis of a leaky integrator circuit using charge transfer synapses.
Abstract
It is shown that a simple leaky integrator (LI) circuit operating in a dynamic mode can allow spatial and temporal summation of weighted synaptic outputs. The circuit incorporates a current mirror configuration to sum charge packets released from charge transfer synapses and an n-channel MOSFET, operating in subthreshold, serves to implement a leakage capability, which sets the decay time for the postsynaptic response. The focus of the paper is to develop an analytical model for fan-in and validate the model against simulation and experimental results obtained from a prototype chip fabricated in the AMS 0.35 µm mixed signal CMOS technology. We show that the model predicts the theoretical limit on fan-in, relates the magnitude of the postsynaptic response to weighted synaptic inputs and captures the transient response of the LI when stimulated with spike inputs.
Year
DOI
Venue
2018
10.1016/j.neucom.2018.06.065
Neurocomputing
Keywords
Field
DocType
Neuromorphic circuits,Fan-in,Spiking neural network,Leaky integrator,Charge transfer synapse,CMOS
Transient response,Topology,Leaky integrator,Pattern recognition,Current mirror,Fan-in,CMOS,Subthreshold conduction,Artificial intelligence,Mixed-signal integrated circuit,Spiking neural network,Mathematics
Journal
Volume
ISSN
Citations 
314
0925-2312
0
PageRank 
References 
Authors
0.34
13
3
Name
Order
Citations
PageRank
Thomas Dowrick1182.47
Liam Mcdaid227030.48
Stephen Hall300.34