Name
Abstract | ||
|---|---|---|
This paper presents a 6-bit 4GS/s current-steering digital-to-analog converter (DAC) for wideband systems. The 4-2 segmented structure is adopted for glitch reduction, and a dynamic decoder is proposed to maintain low power consumption and small area. In order to improve the high-frequency dynamic linearity, the forward-bias technique is employed to reduce the device sizes, and a compact one-dimensional (1-D) current source unit is used to further minimize the parasitic capacitance. The DAC is fabricated in 40-nm low-leakage CMOS process and occupies the active area of 0.036 mm(2). Over the entire Nyquist range, measurement results show a spurious free dynamic range (SFDR) of >39 dB at 2GS/s sampling rate and >29 dB at 4GS/s, respectively. The DAC consumes 28 mW power from 1.1 V supply voltage. |
Year | DOI | Venue |
|---|---|---|
2018 | 10.1587/elex.15.20180660 | IEICE ELECTRONICS EXPRESS |
Keywords | Field | DocType |
CMOS current-steering DAC, dynamic decoder, compact current source unit, forward-bias technique, high dynamic linearity | Computer science,Electronic engineering | Journal |
Volume | Issue | ISSN |
15 | 16 | 1349-2543 |
Citations | PageRank | References |
0 | 0.34 | 6 |
Authors | ||
3 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Bao Li | 1 | 185 | 38.33 |
| Long Zhao | 2 | 78 | 13.96 |
| Yu-Hua Cheng | 3 | 2 | 5.85 |